In electronic applications multi-level polymer structures are being increasingly used, for example, as the top metallization structures of semiconductor chips, semiconductor chip packaging substrates and as independent structures for electrically interconnecting a semiconductor chip to a semiconductor chip substrate. These multi-level polymer structures are used since they can be fabricated independently of the structure on which they are disposed. For example, a semiconductor chip, or a semiconductor chip packaging substrate can be fabricated to a level having a predetermined terminal electrical conductor pattern. A multi-level polymer structure can be fabricated having on a first side an electrical conductor pattern corresponding to the terminal electrical conductor pattern of the chip or substrate. On a second side of the multi-level polymer structure a variety of terminal or input/output conductor patterns can be fabricated. An easily implemented and inexpensive personalization of the semiconductor chip or semiconductor chip packaging substrate is provided by disposing the first side of the multi-level polymer structure onto the chip or substrate.
Semiconductor chip packaging substrates are typically made from ceramic materials having multi-level conductor patterns therein. Electrical conducts in the upper levels are used to electrically interconnect the substrate to the input/output terminals of the semiconductor chip mounted thereon. Therefore, the upper levels require a denser electrical conductor pattern than other levels in the substrate. Patterns of finer dimensions can be fabricated in polymer materials than in the ceramic materials. Therefore, the use of multi-level conductor polymer structures permits the terminal metallization layers of a semiconductor chip packaging substrate to have electrical conductors which have smaller dimensions and which are more closely spaced than is capable of being fabricated in the ceramic material of a ceramic semiconductor chip substrate.
A multi-level polymer structure is typically fabricated by providing a first polymer layer using standard photolithography techniques forming a pattern of through-holes therein which are filled with an electrically conducting material. A second polymer layer is deposited thereover. A resist like material is deposited onto the second polymer layer. The resist like material is patterned and developed exposing regions of the second polymer layer. The exposed polymer regions can be etched by a chemical etchant or a dry etchant, such as, as a reactive ion (RIE) or plasma etchant. For the purpose of this application RIE and plasma etching are synonymous. RIE etching is the preferred etchant since it provides straighter sidewalls to the pattern etched in the polymer layer and thereby forms a pattern having smaller dimensions. The RIE etches down through the second polymer layer and reaches the top surface of the first polymer layer. The RIE etching can be timed in order to stop it at the appropriate depth. Timing the RIE etch results in a variable depth of the etched pattern. The variation in the depth is determined by the accuracy of the timing of the etching as well as statistical variations in the RIE etch parameters. The variation in the etched depth can be eliminated if an RIE etch barrier is provided between the first and second polymer layer. As a pattern is RIE etched in the second polymer layer, the RIE etching stops at the etch barrier, thereby the etched depth is accurately controlled.
The inventions herein are not limited to RIE etch barriers embedded within polymer materials but is generally applicable to such barriers embedded in a dielectric material.
It is an object of this invention to provide a dielectric body having an RIE etch barrier embedded therein.
Multi-level polymer structures used in electronic applications are cycled up to relatively high temperatures, for example, in excess of 400.degree. C. Therefore, RIE etch barrier disposed within a multi-level polymer structure should have high thermal stability.
It is another object of this invention to provide a polymer body having an RIE etch barrier embedded therein.
It is another object of this invention to provide a polymer body having an RIE etch barrier embedded therein which is useful for electronic applications.
It is another object of this invention to provide a polymer body with an RIE etch barrier embedded therein which has high thermal stability.
When an electrical conducting material is deposited into a pattern etched in a dielectric layer, typically there are spaces between the sidewall of the pattern in the dielectric material and the electrical conductor formed therein. Such spaces provide regions where contaminants, for example, created during the processing of the substrate, can accumulate. Contaminants such as ionic contaminants can create electrical short circuits between electrically conducting lines and can result in corrosion of the electrically conducting lines which can result in electrical opens. It is desirable to fill these spaces or gaps to avoid these undesirable effects.
The RIE etch barrier according to the present invention is deposited as a liquid polymer which has a viscosity sufficient to permit the polymer to flow into into the gaps between the electrical conductors and the etched pattern in the dielectric material. The liquid polymer is thereafter cured to cross-link the polymer to a solid state.
It is an object of this invention to provide a polymeric material which fills the gaps between the electrical conductors and the dielectric body within which it is embedded.
Polymeric materials according to the present invention which simultaneously act as a RIE etch barrier and are capable of filling these gaps are formed from a copolymer, one unit of which has high temperature stability and at least one other unit of which is capable of cross-linking the polymer.
It is another object of this invention to provide a polymeric material having a high thermally stable component and a component permitting cross-linking.
RIE etching of substrates for electronic applications frequently use oxygen containing RIE etches. Prior art materials which an artisan might suspect would provide a high resistance to an oxygen RIE or plasma etch suffer from several inadequacies. In the liquid state they have high viscosity mitigating against their ability to fill the gaps, they have low resistance to the oxygen plasma or they have a low thermal stability precluding their use in a high temperature cycling environment such as required as an intermediate layer in a dielectric structure for electronic applications. The RIE etch barrier materials according to the present invention surmount these problems by having a low viscosity and being free of solvents which reduces the problems of shrinkage on curing and by having a high etch resistance with respect to the dielectric body.